ECE 4040/5040: Advanced VLSI and SoC Design

Learning Objectives

By the end of the course, students will be able to:

1. Write synthesizable RTL (modules, FSMs, datapaths) and build self-checking testbenches.
2. Apply timing constraints (SDC) and perform logic synthesis with QoR signoff checks.
3. Construct a floorplan (IOs, macros, power grid), execute timing-/congestion-driven placement, and diagnose hotspots.
4. Build clock trees (buffering, skew/jitter control, routing rules) and reason about insertion delay and useful skew.
5. Route designs and resolve DRC/LVS, crosstalk, and electromigration issues; apply DFM (e.g., wire spreading, multi-cut vias).
6. Run STA (setup/hold, path-based analysis), identify root causes, and close PPA with targeted ECOs.
7. Produce a DRC/LVS-clean, signoff-quality GDSII ready for tapeout; document assumptions, risks, and deliverables.
8. ECE 5040: Evaluate alternative algorithms/flows and justify trade-offs with measured data.

Textbooks

1. Kahng, Lillis, Robins, & Markov, VLSI Physical Design: From Graph Partitioning to Timing Closure.
2. Khosrow Golshan, Physical Design Essentials: An ASIC Design Implementation Perspective.
3. Sherwani, Algorithms for VLSI Physical Design Automation.
4. Khosrow Golshan, The Art of Timing Closure: Advanced ASIC Design Implementation.

Prerequisites

ECE 2400 Digital Logic; ECE 4450 Introduction to VLSI Design; basic HDL (Verilog preferred). Prior exposure to EDA tools is helpful.

EDA Tools

1. Cadence Genus: RTL synthesis, constraints (SDC), tech mapping, synthesis reports.
2. Cadence Innovus: Physical design (floorplan, placement, CTS, routing, post-route optimization).
3. Cadence Tempus: STA signoff (MCMM, OCV/AOCV/POCV), correlation.
4. Cadence Xcelium (or Siemens QuestaSim): simulation, waveform debug, assertions.
5. Siemens Calibre: DRC/LVS/PEX for signoff and parasitic extraction.
6. Recommended: Voltus (IR/EM), Quantus (extraction), Conformal (LEC).

Assessment & Grading

Late Policy: 1 day late = –5%; 2 days late = –15%; > 48 hours late = no credit. Labs are verified live during the session or by submission of logs/reports.

Graduate (ECE 5040) Addendum

1. Implement one research-level extension in the final project (e.g., multi-VDD design, CCOpt analysis, congestion optimization).
2. Submit a 6–7 page double-column IEEE-format paper based on the selected research idea and measured results.

Week‑by‑Week Schedule (Two classes per week)

Lectures meet Tuesday and Friday. Sessions are grouped into modules and follow a tapeout-oriented RTL-to-GDSII flow.

Weekly Lecture Slides

Slides are posted weekly. Click Download to access (password required).

Professional Expectations

• Present solutions clearly with units, diagrams, and step-by-step reasoning.
• Maintain academic integrity and professional conduct in class and lab.
• Follow repo standards and clean hand-off practices for labs and the final tapeout package.

Course Policy on AI & Tools

Do not submit AI-generated answers or designs as your own. If you use tools for brainstorming, formatting, or debugging help, cite the tool usage and keep all graded deliverables consistent with course policy and academic integrity rules.